There are 4 stable states and 12 states that are transistional between stable states in normal operation. I will provide this information, but not as a diagram. For example, the OPs circuit, shows up all over the place labeled as a T flip-flop despite the fact that it has problems described in other answers.) However, I am offering the above information as an alternative point of view to that of the commenter.Įdit2: A commenter has asked for a state diagram for the circuit. (There is certainly a lot of misinformation about flip-flops on the interwebs.

I don't claim that this is necessarily an authoritative refutation of the claim that a T flip-flop must have separate T and clock inputs. It can be made from a J-K flip-flop by tying both of its inputs high. It is useful for constructing binary counters, frequency dividers, and general binary addition devices. The T or 'toggle' flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. However, when I google 'T flip-flop', the very first hit that comes up for me is this which states: Someone has commented that this circuit is not a T flip-flop because the circuit depends upon the clock alone, and does not have separate T and clock inputs. Simulate this circuit – Schematic created using CircuitLab The circuit below simulates fine in CircuitLab.

To implement an edge triggered T Flip-Flop that does not rely on gate delay timing, requires, I believe, a minimum of 6 Nand gates.

Multisim jk flip flop